Field of the Invention
The invention relates in general to a phase detector, and more particularly to an asynchronous phase detector applied in a clock and data recovery circuit.
Description of the Related Art
A data stream received by an optical or wireless receiver is both asynchronous and noisy. For subsequent processing, timing information, e.g., a clock, must be extracted from the data stream so as to allow synchronous operations. Furthermore, the data stream must be “retimed” such that the jitter accumulated during transmission is removed. To complete the task of clock extraction and data retiming, “clock and data recovery” (CDR) circuits are extensively applied in optical or wireless receivers.
FIG. 1 shows a diagram of data eye patterns and several sampling instants of a data stream. FIG. 2 shows correspondence between inputs and outputs of an Alexander phase detector. According to a local clock signal, an Alexander phase detector oversamples an input signal carrying a data stream at sampling instants A, B and C at a rate approximately twice a symbol rate of the input signal to generate signal samples DA, DB and DC, respectively. For transmission speed considerations, input signals are generally coded in nonreturn-to-zero (NRZ) format. When the local clock signal is approximately synchronous with the timing of the data stream, the sampling instants A, B and C are spaced by a half of a symbol period from one another, and the sampling instant B is approximately located near an intersection between two eyes of the data eye patterns. For example, if the signal samples DA, DB and DC are respectively logic “0”, “0” and “1”, it means that the sampling instant B is earlier than the intersection between two eyes of the data eye patterns. Thus, as shown in FIG. 2, the output of the Alexander phase detector should slow down the clock frequency fCLK of the local clock signal such that the subsequent sampling instant B may approach the intersection.
FIG. 2 shows pre XOR operation results of signal samples DA and DB and post-XOR operation results of signal samples DB and DC. When the pre XOR operation result and the post XOR operation result are respectively “0” and “1”, the clock frequency fCLK of the local clock signal is expected to slow down. When the pre XOR operation result and the post XOR operation result are respectively “0” and “0”, it means that the signal samples are the same logic values, and the sequence relationship between the intersection and the sampling instant B cannot be learned. Thus, the clock frequency of the local clock signal is kept unchanged. When the pre XOR operation result and the post XOR operation result are respectively “1” and “0”, the clock frequency of the local clock signal is expected to increase. When the pre XOR operation result and the post XOR operation result are respectively “1” and “1”, it means that there are two intersections between the sampling instants A and C, and such occurrence is fundamentally unexpected to happen. At this point, the clock frequency fCLK may react according to the definition of the circuit designer.